100 lines
4.3 KiB
Plaintext
100 lines
4.3 KiB
Plaintext
// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/05/CPU.hdl
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/**
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* The Hack CPU (Central Processing unit), consisting of an ALU,
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* two registers named A and D, and a program counter named PC.
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* The CPU is designed to fetch and execute instructions written in
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* the Hack machine language. In particular, functions as follows:
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* Executes the inputted instruction according to the Hack machine
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* language specification. The D and A in the language specification
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* refer to CPU-resident registers, while M refers to the external
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* memory location addressed by A, i.e. to Memory[A]. The inM input
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* holds the value of this location. If the current instruction needs
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* to write a value to M, the value is placed in outM, the address
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* of the target location is placed in the addressM output, and the
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* writeM control bit is asserted. (When writeM==0, any value may
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* appear in outM). The outM and writeM outputs are combinational:
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* they are affected instantaneously by the execution of the current
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* instruction. The addressM and pc outputs are clocked: although they
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* are affected by the execution of the current instruction, they commit
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* to their new values only in the next time step. If reset==1 then the
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* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
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* than to the address resulting from executing the current instruction.
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*/
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CHIP CPU {
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IN inM[16], // M value input (M = contents of RAM[A])
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instruction[16], // Instruction for execution
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reset; // Signals whether to re-start the current
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// program (reset==1) or continue executing
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// the current program (reset==0).
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OUT outM[16], // M value output
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writeM, // Write to M?
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addressM[15], // Address in data memory (of M)
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pc[15]; // address of next instruction
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PARTS:
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/* Instruction bits ixxaccccccdddjjj */
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/* i[15]: 0 -> A-Instruction; 1 -> C-Instruction; */
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Id(in=instruction[15], out=selins);
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Not(in=selins, out=selains);
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Id(in=selins, out=selcins);
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/* i[14..13]: don't care */
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/* i[12]: 0 -> load A into ALU; 1 -> load M into ALU; */
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Id(in=instruction[12], out=selaluinput);
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/* i[11..6]: ALU configuration */
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/* i[5..3]: target memory select*/
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Id(in=instruction[5], out=sela);
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Id(in=instruction[4], out=seld);
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Id(in=instruction[3], out=selm);
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/* i[2..0]: JMP configuration */
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Id(in=instruction[2], out=seljlt);
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Id(in=instruction[1], out=seljeq);
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Id(in=instruction[0], out=seljgt);
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/* If selin = 0 -> A-Instruction -> Address; if selin = 1 -> C-Instruction -> ALU output; */
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Mux16(a=instruction, b=aluout, sel=selins, out=amuxout);
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/* Load A register if it is an A-Instruction or if A is a dest register. */
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Or(a=selains, b=sela, out=loada);
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ARegister(in=amuxout, load=loada, out=aout);
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/* Load D register if it is a C-Instruction and if D is selected. */
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And(a=selcins, b=seld, out=loadd);
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DRegister(in=aluout, load=loadd, out=dout);
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/* Write M register if it is C-Instruction and if M is selected. */
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And(a=selcins, b=selm, out=writeM);
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/* If selaluinput = 0 input A into ALU, otherwise, load M into ALU. */
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Mux16(a=aout, b=inM, sel=selaluinput, out=mmuxout);
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ALU(x=dout, y=mmuxout, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=aluout, zr=zrout, ng=ngout);
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/*
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IN x[16], y[16], // 16-bit inputs zx, nx, zy, ny, f, no;
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OUT out[16], // 16-bit output zr, // 1 if (out == 0), 0 otherwise ng; // 1 if (out < 0), 0 otherwise
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*/
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/* Magic to decided whether we jump or not. */
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And(a=seljlt, b=ngout, out=seljumpjlt);
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And(a=seljeq, b=zrout, out=seljumpjeq);
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Nor(a=ngout, b=zrout, out=positiveout);
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And(a=seljgt, b=positiveout, out=seljumpjgt);
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Or(a=seljumpjlt, b=seljumpjeq, out=seljump1);
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Or(a=seljump1, b=seljumpjgt, out=seljump2);
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And(a=seljump2, b=selcins, out=seljump);
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PC(in=aout, load=seljump, inc=true, reset=reset, out[0..14]=pc);
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Id16(in=aluout, out=outM);
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Id16(in=aout, out[0..14]=addressM);
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}
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