Add solutions for part 1

projects/05/CPU.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/05/CPU.hdl
+
+/**
+ * The Hack CPU (Central Processing unit), consisting of an ALU,
+ * two registers named A and D, and a program counter named PC.
+ * The CPU is designed to fetch and execute instructions written in
+ * the Hack machine language. In particular, functions as follows:
+ * Executes the inputted instruction according to the Hack machine
+ * language specification. The D and A in the language specification
+ * refer to CPU-resident registers, while M refers to the external
+ * memory location addressed by A, i.e. to Memory[A]. The inM input
+ * holds the value of this location. If the current instruction needs
+ * to write a value to M, the value is placed in outM, the address
+ * of the target location is placed in the addressM output, and the
+ * writeM control bit is asserted. (When writeM==0, any value may
+ * appear in outM). The outM and writeM outputs are combinational:
+ * they are affected instantaneously by the execution of the current
+ * instruction. The addressM and pc outputs are clocked: although they
+ * are affected by the execution of the current instruction, they commit
+ * to their new values only in the next time step. If reset==1 then the
+ * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
+ * than to the address resulting from executing the current instruction.
+ */
+
+CHIP CPU {
+
+    IN  inM[16],         // M value input  (M = contents of RAM[A])
+        instruction[16], // Instruction for execution
+        reset;           // Signals whether to re-start the current
+                         // program (reset==1) or continue executing
+                         // the current program (reset==0).
+
+    OUT outM[16],        // M value output
+        writeM,          // Write to M?
+        addressM[15],    // Address in data memory (of M)
+        pc[15];          // address of next instruction
+
+    PARTS:
+
+    /* Instruction bits ixxaccccccdddjjj */
+
+    /* i[15]: 0 -> A-Instruction; 1 -> C-Instruction; */
+    Id(in=instruction[15], out=selins);
+    Not(in=selins, out=selains);
+    Id(in=selins, out=selcins);
+    /* i[14..13]: don't care */
+    /* i[12]: 0 -> load A into ALU; 1 -> load M into ALU; */
+    Id(in=instruction[12], out=selaluinput);
+    /* i[11..6]: ALU configuration */
+    /* i[5..3]: target memory select*/
+    Id(in=instruction[5], out=sela);
+    Id(in=instruction[4], out=seld);
+    Id(in=instruction[3], out=selm);
+    /* i[2..0]: JMP configuration */
+    Id(in=instruction[2], out=seljlt);
+    Id(in=instruction[1], out=seljeq);
+    Id(in=instruction[0], out=seljgt);
+
+    /* If selin = 0 -> A-Instruction -> Address; if selin = 1 -> C-Instruction -> ALU output; */
+    Mux16(a=instruction, b=aluout, sel=selins, out=amuxout);
+
+    /* Load A register if it is an A-Instruction or if A is a dest register. */
+    Or(a=selains, b=sela,  out=loada);
+    ARegister(in=amuxout, load=loada, out=aout);
+
+    /* Load D register if it is a C-Instruction and if D is selected. */
+    And(a=selcins, b=seld, out=loadd);
+    DRegister(in=aluout, load=loadd, out=dout);
+
+    /* Write M register if it is C-Instruction and if M is selected. */
+    And(a=selcins, b=selm, out=writeM);
+
+    /* If selaluinput = 0 input A into ALU, otherwise, load M into ALU.  */
+    Mux16(a=aout, b=inM, sel=selaluinput, out=mmuxout);
+
+    ALU(x=dout, y=mmuxout, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=aluout, zr=zrout, ng=ngout);
+    /*
+    IN x[16], y[16],  // 16-bit inputs zx, nx, zy, ny, f, no;
+    OUT out[16], // 16-bit output zr, // 1 if (out == 0), 0 otherwise ng; // 1 if (out < 0),  0 otherwise
+    */
+
+    /* Magic to decided whether we jump or not. */
+    And(a=seljlt, b=ngout, out=seljumpjlt);
+    And(a=seljeq, b=zrout, out=seljumpjeq);
+    Nor(a=ngout, b=zrout, out=positiveout);
+    And(a=seljgt, b=positiveout, out=seljumpjgt);
+
+    Or(a=seljumpjlt, b=seljumpjeq, out=seljump1);
+    Or(a=seljump1, b=seljumpjgt, out=seljump2);
+    And(a=seljump2, b=selcins, out=seljump);
+
+    PC(in=aout, load=seljump, inc=true, reset=reset, out[0..14]=pc);
+
+    Id16(in=aluout, out=outM);
+    Id16(in=aout, out[0..14]=addressM);
+}