Add solutions for part 1

projects/03/b/RAM4K.hdl

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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM4K.hdl
+
+/**
+ * Memory of 4K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then
+ * the in value is loaded into the memory location specified by address
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM4K {
+    IN in[16], load, address[12];
+    OUT out[16];
+
+    PARTS:
+    DMux8Way(in=load, sel=address[9..11], a=s0, b=s1, c=s2, d=s3, e=s4, f=s5, g=s6, h=s7);
+
+    RAM512(in=in, load=s0, address=address[0..8], out=r0s);
+    RAM512(in=in, load=s1, address=address[0..8], out=r1s);
+    RAM512(in=in, load=s2, address=address[0..8], out=r2s);
+    RAM512(in=in, load=s3, address=address[0..8], out=r3s);
+    RAM512(in=in, load=s4, address=address[0..8], out=r4s);
+    RAM512(in=in, load=s5, address=address[0..8], out=r5s);
+    RAM512(in=in, load=s6, address=address[0..8], out=r6s);
+    RAM512(in=in, load=s7, address=address[0..8], out=r7s);
+
+    Mux8Way16(a=r0s, b=r1s, c=r2s, d=r3s, e=r4s, f=r5s, g=r6s, h=r7s, sel=address[9..11], out=out);
+}