256 lines
7.2 KiB
Scheme
256 lines
7.2 KiB
Scheme
(load "util.scm")
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(load "misc/agenda.scm")
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(load "misc/queue.scm")
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(display "\nexample - simulator of digital circuits\n")
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(define (call-each procedures)
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(if (null? procedures)
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'done
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(begin
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((car procedures))
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(call-each (cdr procedures)))))
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(define (make-wire)
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(let ((signal-value 0) (action-procedures '()))
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(define (set-my-signal! new-value)
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(if (not (= signal-value new-value))
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(begin (set! signal-value new-value)
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(call-each action-procedures))
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'done))
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(define (accept-action-procedure! proc)
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(set! action-procedures (cons proc action-procedures))
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(proc))
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(define (dispatch m)
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(cond ((eq? m 'get-signal) signal-value)
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((eq? m 'set-signal!) set-my-signal!)
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((eq? m 'add-action!) accept-action-procedure!)
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(else (error "Unknown operation -- WIRE" m))))
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dispatch))
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(define (probe name wire)
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(add-action! wire
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(lambda ()
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(newline)
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(display name)
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(display " ")
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(display (current-time the-agenda))
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(display " New-value = ")
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(display (get-signal wire)))))
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(define (get-signal wire)
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(wire 'get-signal))
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(define (set-signal! wire new-value)
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((wire 'set-signal!) new-value))
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(define (add-action! wire action-procedure)
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((wire 'add-action!) action-procedure))
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(define the-agenda (make-agenda))
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(define inverter-delay 2)
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(define and-gate-delay 3)
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(define or-gate-delay 5)
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(define (logical-not s)
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(cond ((= s 0) 1)
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((= s 1) 0)
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(else (error "NOT - invalid signal" s))))
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(define (logical-and s1 s2)
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(cond ((and (= s1 0) (= s2 0)) 0)
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((and (= s1 0) (= s2 1)) 0)
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((and (= s1 1) (= s2 0)) 0)
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((and (= s1 1) (= s2 1)) 1)
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(else (error "AND - invalid signal"))))
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(define (logical-or s1 s2)
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(cond ((and (= s1 0) (= s2 0)) 0)
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((and (= s1 0) (= s2 1)) 1)
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((and (= s1 1) (= s2 0)) 1)
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((and (= s1 1) (= s2 1)) 1)
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(else (error "OR - invalid signal"))))
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(define (half-adder a b s c)
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(let ((d (make-wire)) (e (make-wire)))
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(or-gate a b d)
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(and-gate a b c)
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(inverter c e)
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(and-gate d e s)
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'ok))
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(define (full-adder a b c-in sum c-out)
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(let ((s (make-wire))
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(c1 (make-wire))
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(c2 (make-wire)))
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(half-adder b c-in s c1)
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(half-adder a s sum c2)
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(or-gate c1 c2 c-out)
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'ok))
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(define (inverter input output)
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(define (invert-input)
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(let ((new-value (logical-not (get-signal input))))
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(after-delay inverter-delay
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(lambda ()
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(set-signal! output new-value)))))
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(add-action! input invert-input)
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'ok)
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(define (and-gate a1 a2 output)
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(define (and-action-procedure)
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(let ((new-value
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(logical-and (get-signal a1) (get-signal a2))))
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(after-delay and-gate-delay
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(lambda ()
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(set-signal! output new-value)))))
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(add-action! a1 and-action-procedure)
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(add-action! a2 and-action-procedure)
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'ok)
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(assert (logical-and 1 0) 0)
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(assert (logical-and 1 1) 1)
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(display "\nex-3.28 - or-gate\n")
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(define (or-gate a1 a2 output)
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(define (or-action-procedure)
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(let ((new-value
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(logical-or (get-signal a1) (get-signal a2))))
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(after-delay or-gate-delay
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(lambda ()
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(set-signal! output new-value)))))
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(add-action! a1 or-action-procedure)
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(add-action! a2 or-action-procedure)
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'ok)
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(assert (logical-or 0 1) 1)
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(assert (logical-or 1 1) 1)
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(display "\nex-3.29 - or-gate via and-gate and inverter\n")
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(define (nand-gate a1 a2 output)
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(let ((b (make-wire)))
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(and-gate a1 a2 b)
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(inverter b output)
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'ok))
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(define (or-gate-via a1 a2 output)
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(let ((na1 (make-wire)) (na2 (make-wire)))
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(inverter a1 na1)
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(inverter a2 na2)
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(nand-gate na1 na2 output)
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'ok))
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; The or-gate has three inverter delays and one and-gate delay. The first two
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; inverters can run in parallel so if we implement after-delay correct the
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; total delay should only be two inverter delays and one and-gate delay.
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(define a (make-wire))
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(define b (make-wire))
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(define out (make-wire))
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;(probe 'out out)
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(or-gate-via a b out)
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(set-signal! a 1)
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(set-signal! b 1)
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(propagate)
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(assert (get-signal out) 1)
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(set-signal! a 0)
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(set-signal! b 0)
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(propagate)
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(assert (get-signal out) 0)
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(display "\nex-3.30 - ripple-carry-adder\n")
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; Each full-adder has a delay of three or-gates, four and-gates and two
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; inverters. Again, some of chips in the half-adder could run in parallel, so
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; if after-delay is implemented accordingly the time will be shorter. The delay
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; of the ripple-carry-adder is the delay of the full-adder times the number of
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; input signals n.
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(define (ripple-carry-adder as bs ss c)
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(define c-in (make-wire))
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(define (wire-ripple-carry-adder as bs ss c-in)
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(let ((ak (car as)) (bk (car bs))
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(sk (car ss)) (ck (make-wire)))
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(if (null? (cdr ss))
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(full-adder ak bk c-in sk c)
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(begin
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(full-adder ak bk c-in sk ck)
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(wire-ripple-carry-adder
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(cdr as) (cdr bs) (cdr ss) ck)))))
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(wire-ripple-carry-adder as bs ss c-in))
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(let ((a1 (make-wire)) (a2 (make-wire)) (a3 (make-wire))
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(b1 (make-wire)) (b2 (make-wire)) (b3 (make-wire))
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(s1 (make-wire)) (s2 (make-wire)) (s3 (make-wire))
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(co (make-wire)))
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(ripple-carry-adder (list a1 a2 a3) (list b1 b2 b3) (list s1 s2 s3) co)
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(set-signal! a1 1)
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(set-signal! a2 1)
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(set-signal! a3 1)
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(set-signal! b1 1)
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(set-signal! b2 1)
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(set-signal! b3 0)
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(propagate)
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(assert (get-signal s1) 0)
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(assert (get-signal s2) 1)
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(assert (get-signal s3) 0)
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(assert (get-signal co) 1))
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(display "\nex-3.31 - accept-action-procedure!\n")
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(display "[see comment]\n")
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(define input-1 (make-wire))
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(define input-2 (make-wire))
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(define sum (make-wire))
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(define carry (make-wire))
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; (probe 'sum sum)
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; (probe 'carry carry)
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(set-signal! input-1 1)
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(set-signal! input-2 1)
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(half-adder input-1 input-2 sum carry)
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(propagate)
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(assert (get-signal sum) 0)
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(assert (get-signal carry) 1)
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; It is necessary to call the action procedure upon the initialization of the
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; gate to make sure that all wires are set to their correct value initially.
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; For the example with the half-adder the carry-bit stays at zero because the
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; AND-gate is not initialized to the correct value for two 1s as input. To
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; avoid the issue we would have to make sure that each signal changes at least
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; one.
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(display "\nex-3.32\n")
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(display "[see comment]\n")
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(define input-1 (make-wire))
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(define input-2 (make-wire))
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(define out (make-wire))
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(and-gate input-1 input-2 out)
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; (probe 'out out)
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(set-signal! input-1 0)
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(set-signal! input-2 1)
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(propagate)
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(assert (get-signal out) 0)
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(set-signal! input-1 1)
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(set-signal! input-2 0)
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(propagate)
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(assert (get-signal out) 0)
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; Executing the queued action items out of order could lead to unexpected
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; states. In the example above, if we set input-1 to 1 first, and then input-2
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; to 0, we would expect the output to change to 1 for one and-gate-delay. If we
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; probe the output signal we can see that this is indeed what happens. Now, if
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; the actions would not be processed in FIFO order, the output would never
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; switch to 1.
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